View AD9230-11_4352031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

11-Bit, 200 MSPS, 1.8 V Analog-to-Digital Converter AD9230-11
FEATURES
SNR = 62.5 dBFS @ fIN up to 70 MHz @ 200 MSPS ENOB of 10.2 @ fIN up to 70 MHz @ 200 MSPS (-1.0 dBFS) SFDR = -77 dBc @ fIN up to 70 MHz @ 200 MSPS (-1.0 dBFS) Excellent linearity DNL = 0.15 LSB typical INL = 0.5 LSB typical LVDS at 200 MSPS (ANSI-644 levels) 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold amplifier Low power dissipation 373 mW @ 200 MSPS (LVDS SDR mode) 328 mW @ 200 MSPS (LVDS DDR mode) Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos complement, gray code) Clock duty cycle stabilizer Integrated data capture clock
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN AGND AVDD
REFERENCE CML VIN+ VIN- TRACK-AND-HOLD ADC 12-BIT CORE CLK+ CLK- CLOCK MANAGEMENT 12
AD9230-11
DRVDD DRGND
OUTPUT STAGING LVDS
11
D10 TO D0
OR+ OR- SERIAL PORT DCO+
07101-001
DCO- RESET SCLK SDIO CSB
Figure 1.
APPLICATIONS
Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization
GENERAL DESCRIPTION
The AD9230-11 is an 11-bit monolithic sampling analog-todigital converter (ADC) optimized for high performance, low power, and ease of use. The product operates at up to a 200 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) amplifier and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9230-11 is available in a 56-lead lead frame chip scale package, specified over the industrial temperature range (-40C to +85C).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. 2. 3. High Performance. Maintains 62.5 dBFS SNR @ 200 MSPS with a 70 MHz input. Low Power. Consumes only 373 mW @ 200 MSPS. Ease of Use. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface (SPI) supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family. 10-bit and 12-bit pin-compatible family offered as AD9211 and AD9230.
4.
5.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD9230-11 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 13 Equivalent Circuits ......................................................................... 15 Theory of Operation ...................................................................... 16 Analog Input and Voltage Reference ....................................... 16 Clock Input Considerations ...................................................... 17 Power Dissipation and Power-Down Mode ........................... 18 Digital Outputs ........................................................................... 18 Timing ......................................................................................... 19 RBIAS ........................................................................................... 19 Configuration Using the SPI ..................................................... 19 Hardware Interface..................................................................... 20 Configuration Without the SPI ................................................ 20 Memory Map .................................................................................. 22 Reading the Memory Map Table .............................................. 22 Reserved Locations .................................................................... 22 Default Values ............................................................................. 22 Logic Levels ................................................................................. 22 Transfer Register Map ................................................................ 22 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD9230-11 SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 1.
Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error ANALOG INPUTS (VIN+, VIN-) Differential Input Voltage Range 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance POWER SUPPLY AVDD DRVDD Supply Currents IAVDD 3 IDRVDD3/SDR Mode 4 IDRVDD3/DDR Mode 5 Power Dissipation3 SDR Mode4 DDR Mode5
1
Temp
Min
Typ 11 Guaranteed 4.2
Max
Unit Bits
Full 25C Full 25C Full 25C Full 25C Full Full Full Full Full Full 25C Full Full Full Full Full Full Full Full
-12 0.89 -2.2 0.15 -0.4 0.5 -0.5 9 0.019 0.98 1.25 1.4 4.3 2 1.8 1.8 152 55 36 373 338
+12 +4.3 +0.4 +0.5
mV mV % FS % FS LSB LSB LSB LSB V/C %/C
1.5
V p-p V k pF V V mA mA mA mW mW
1.7 1.7
1.9 1.9 164 58
400
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section. 3 IAVDD and IDRVDD are measured with a -1 dBFS, 10.3 MHz sine input at rated sample rate. 4 Single data rate mode; this is the default mode of the AD9230-11. 5 Double data rate mode; user-programmable feature. See the Memory Map section.
Rev. 0 | Page 3 of 28
AD9230-11
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. 1 Table 2.
Parameter 2 SNR fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz SINAD fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz WORST OTHER (SFDR EXCLUDING SECOND AND THIRD) fIN = 10 MHz fIN = 70 MHz fIN = 170 MHz ANALOG INPUT BANDWIDTH
1 2
Temp 25C Full 25C Full 25C 25C Full 25C Full 25C 25C 25C 25C 25C Full 25C Full 25C 25C Full 25C Full 25C 25C
Min 62.4 62.2 62.2 62.0
Typ 62.9 62.5 61.8
Max
Unit dB dB dB dB dB dB dB dB dB dB Bits Bits Bits
62.3 62.1 62.0 61.8
62.8 62.3 61.5 10.3 10.2 10.1 -86 -79 -76 -88 -84 -82 700 -84 -79 -82 -81 -77 -77 -77 -76
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz
All ac specifications tested by driving CLK+ and CLK- differentially. See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed.
Rev. 0 | Page 4 of 28
AD9230-11
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 3.
Parameter 1 CLOCK INPUTS Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance (Differential) Input Capacitance LOGIC INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current (SDIO) Logic 0 Input Current (SDIO) Logic 1 Input Current (SCLK, PWDN, CSB, RESET) Logic 0 Input Current (SCLK, PWDN, CSB, RESET) Input Capacitance LOGIC OUTPUTS 2 VOD Differential Output Voltage VOS Output Offset Voltage Output Coding
1
Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C Full Full
Min
Typ
Max
Unit
0.2 AGND - 0.3 1.1 1.2 0 -10 -10 16
CMOS/LVDS/LVPECL 1.2 6 AVDD + 1.6 AVDD 3.6 0.8 +10 +10 20 24 4
V V p-p V V V V A A k pF V V A A A A pF mV V
0.8 x AVDD 0.2 x AVDD 0 -60 55 0 4 247 454 1.125 1.375 Twos complement, gray code, or offset binary (default)
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and an explanation of how these tests were completed. 2 LVDS RTERMINATION = 100 .
Rev. 0 | Page 5 of 28
AD9230-11
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = -40C, TMAX = +85C, fIN = -1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted. Table 4.
Parameter CONVERSION RATE Maximum Conversion Rate Minimum Conversion Rate PULSE WIDTH CLK+ Pulse Width High (tCH) CLK+ Pulse Width Low (tCL) OUTPUT (LVDS, SDR MODE) 1 Data Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tSKEW) Latency OUTPUT (LVDS, DDR MODE) 2 Data Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) DCO Propagation Delay (tCPD) Data to DCO Skew (tSKEW) Latency APERTURE UNCERTAINTY (JITTER, tJ)
1 2
Temp Full Full Full Full Full 25C 25C Full Full Full Full 25C 25C Full Full Full 25C
Min 200
Typ
Max
Unit MSPS MSPS ns ns ns ns ns ns ns Cycles ns ns ns ns ns Cycles ps rms
40 2.25 2.25 2.5 2.5 3.8 0.2 0.2 3.9 0.1 6 3.8 0.2 0.2 3.9 0.1 6 0.2
-0.3
0.5
-0.5
0.3
See Figure 2. See Figure 3.
Rev. 0 | Page 6 of 28
AD9230-11
TIMING DIAGRAMS
N-1 N VIN N+1 N+3
tA
N+4 N+5
N+2
tCH
CLK+ CLK-
tCL
1/fS
tCPD
DCO+ DCO-
tSKEW tPD
Dx+ Dx-
07101-002
07101-003
N-6
N-5
N-4
N-3
N-2
Figure 2. Single Data Rate Mode
N-1 N VIN
tA
N+3
N+4 N+5
N+1
N+2
tCH
CLK+ CLK-
tCL
1/fS
tCPD
DCO+ DCO-
tSKEW tPD
D5+ D5- D5 N-7 NO DATA D5 N-6 NO DATA D5 N-5 NO DATA D5 N-4 NO DATA D5 N-3 NO DATA
D4/D10+ D4/D10-
D10 N-7 6 MSBs
D4 N-6 5 LSBs
D10 N-6
D4 N-5
D10 N-5
D4 N-4
D10 N-4
D4 N-3
D10 N-3
D4 N-2
Figure 3. Double Data Rate Mode
Rev. 0 | Page 7 of 28
AD9230-11 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Electrical AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD D0+/D0- through D10+/D10- to DRGND DCO+/DCO- to DRGND OR+/OR- to DGND CLK+ to AGND CLK- to AGND VIN+ to AGND VIN- to AGND SDIO/DCS to DGND PWDN to AGND CSB to AGND SCLK/DFS to AGND Environmental Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to DRVDD + 0.3 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to AVDD + 0.2 V -0.3 V to AVDD + 0.2 V -0.3 V to DRVDD + 0.3 V -0.3 V to +3.9 V -0.3 V to +3.9 V -0.3 V to +3.9 V -65C to +125C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6.
Package Type 56-Lead LFCSP (CP-56-2) JA 30.4 JC 2.9 Unit C/W
Typical JA and JC are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing JA. In addition, metal that is in direct contact with the package leads reduces the JA.
ESD CAUTION
Rev. 0 | Page 8 of 28
AD9230-11 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
56 55 54 53 52 51 50 49 48 47 46 45 44 43
D2- D2+ D3- D3+ D4- D4+ DRVDD DRGND D5- D5+ D6- D6+ D7- D7+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29
D1+ D1- D0+ (LSB) D0- (LSB) DNC DNC DCO+ DCO- DRGND DRVDD AVDD CLK- CLK+ AVDD
PIN 1 INDICATOR
AD9230-11
TOP VIEW (Not to Scale)
AVDD AVDD CML AVDD AVDD AVDD VIN- VIN+ AVDD AVDD AVDD RBIAS AVDD PWDN
Figure 4. Single Data Rate Mode Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No. 30, 32 to 34, 37 to 39, 41 to 43, 46 7, 24, 47 0 8, 23, 48 35 36 40 44 45 31 28 25 26 27 29 49 50 51, 52 53 54 55 56 1 2 Mnemonic AVDD DRVDD AGND 1 DRGND1 VIN+ VIN- CML CLK+ CLK- RBIAS RESET SDIO/DCS SCLK/DFS CSB PWDN DCO- DCO+ DNC D0- (LSB) D0+ (LSB) D1- D1+ D2- D2+ Description 1.8 V Analog Supply. 1.8 V Digital Output Supply. Analog Ground. The exposed paddle should be connected to the analog ground. Digital Output Ground. Analog Input (True). Analog Input (Complement). Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN-. Clock Input (True). Clock Input (Complement). Set Pin for Chip Bias Current. Place 1% 10 k resistor terminated to ground. Nominally 0.5 V. CMOS-Compatible Chip Reset (Active Low). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Duty Cycle Stabilizer Select (External Pin Mode). Serial Port Interface Clock (Serial Port Mode). Data Format Select Pin (External Pin Mode). Serial Port Chip Select (Active Low). Chip Power-Down. Data Clock Output (Complement). Data Clock Output Input (True). Do No Connect. D0 Complement Output Bit (LSB). D0 True Output Bit (LSB). D1 Complement Output Bit. D1 True Output Bit. D2 Complement Output Bit. D2 True Output Bit.
Rev. 0 | Page 9 of 28
07101-004
NOTES 1. DNC = DO NOT CONNECT. 2. PIN 0 (EXPOSED PADDLE) = AGND.
D8- D8+ D9- D9+ (MSB) D10- (MSB) D10+ OR- OR+ DRGND DRVDD SDIO/DCS SCLK/DFS CSB RESET
15 16 17 18 19 20 21 22 23 24 25 26 27 28
AD9230-11
Pin No. 3 4 5 6 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
Mnemonic D3- D3+ D4- D4+ D5- D5+ D6- D6+ D7- D7+ D8- D8+ D9- D9+ D10- (MSB) D10+ (MSB) OR- OR+
Description D3 Complement Output Bit. D3 True Output Bit. D4 Complement Output Bit. D4 True Output Bit. D5 Complement Output Bit. D5 True Output Bit. D6 Complement Output Bit. D6 True Output Bit. D7 Complement Output Bit. D77 True Output Bit. D8 Complement Output Bit. D8 True Output Bit. D9 Complement Output Bit. D9 True Output Bit. D10 Complement Output Bit (MSB). D10 True Output Bit (MSB). Overrange Complement Output Bit. Overrange True Output Bit.
AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 10 of 28
AD9230-11
D1/D7+ D1/D7- D0/D6+ (LSB) D0/D6- (LSB) ND/D5+ ND/D5- DCO+ DCO- DRGND DRVDD AVDD CLK- CLK+ AVDD
D2/D8- D2/D8+ D3/D9- D3/D9+ (MSB) D4/D10- (MSB) D4/D10+ DRVDD DRGND OR- OR+ DNC DNC DNC DNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42 41 40 39 38 37 36 35 34 33 32 31 30 29
PIN 1 INDICATOR
AD9230-11
TOP VIEW (Not to Scale)
AVDD AVDD CML AVDD AVDD AVDD VIN- VIN+ AVDD AVDD AVDD RBIAS AVDD PWDN
Figure 5. Double Data Rate Mode Pin Configuration
Table 8. Double Data Rate Mode Pin Function Descriptions
Pin No. 30, 32 to 34, 37 to 39, 41 to 43, 46 7, 24, 47 0 8, 23, 48 35 36 40 44 45 31 28 25 26 27 29 49 50 51 52 53 54 55 56 1 2 Mnemonic AVDD DRVDD AGND 1 DRGND1 VIN+ VIN- CML CLK+ CLK- RBIAS RESET SDIO/DCS SCLK/DFS CSB PWDN DCO- DCO+ ND/D5- ND/D5+ D0/D6- (LSB) D0/D6+ (LSB) D1/D7- D1/D7+ D2/D8- D2/D8+ Description 1.8 V Analog Supply. 1.8 V Digital Output Supply. Analog Ground. The exposed paddle should be connected to the analog ground. Digital Output Ground. Analog Input Input (True). Analog Input (Complement). Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the optimized internal bias voltage for VIN+/VIN-. Clock Input Input (True). Clock Input (Complement). Set Pin for Chip Bias Current. Place 1% 10 k resistor terminated to ground. Nominally 0.5 V. CMOS-Compatible Chip Reset (Active Low). Serial Port Interface (SPI) Data Input/Output (Serial Port Mode). Duty Cycle Stabilizer Select (External Pin Mode). Serial Port Interface Clock (Serial Port Mode). Data Format Select Pin (External Pin Mode). Serial Port Chip Select (Active Low). Chip Power-Down. Data Clock Output (Complement). Data Clock Output Input (True). ND/D5 Complement Output Bit. ND/D5 True Output Bit. D0/D6 Complement Output Bit (LSB). D0/D6 True Output Bit (LSB). D1/D7 Complement Output Bit. D1/D7 True Output Bit. D2/D8 Complement Output Bit. D2/D8 True Output Bit.
Rev. 0 | Page 11 of 28
07101-005
NOTES 1. DNC = DO NOT CONNECT. 2. PIN 0 (EXPOSED PADDLE) = AGND.
DNC DNC DNC DNC DNC DNC DNC/(OR-) DNC/(OR+) DRGND DRVDD SDIO/DCS SCLK/DFS CSB RESET
15 16 17 18 19 20 21 22 23 24 25 26 27 28
AD9230-11
Pin No. 3 4 5 6 9 10 11 to 20 21 22
1
Mnemonic D3/D9- D3/D9+ D4/D10- (MSB) D4/D10+ (MSB) OR- OR+ DNC DNC/(OR-) DNC/(OR+)
Description D3/D9 Complement Output Bit. D3/D9 True Output Bit. D4/D10 Complement Output Bit (MSB). D4/D10 True Output Bit (MSB). OR Complement Output Bit. This pin is disabled if Pin 21 is reconfigured through the SPI to be OR-. OR True Output Bit. This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+. Do Not Connect. Do Not Connect. This pin can be reconfigured as the Overrange Complement Output Bit through the serial port register. Do Not Connect. This pin can be reconfigured as the Overrange True Output Bit through the serial port register.
AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 12 of 28
AD9230-11 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25C, 1.25 V p-p differential input, AIN = -1 dBFS, unless otherwise noted.
0 -20 -40 -60 -80 -100 -120 -140 200MSPS 10.3MHz @ -1.0dBFS SNR: 62.9dB ENOB: 10.3 BITS SFDR: 86dBc 85 80 75 SNR (dB) +85C
AMPLITUDE (dBFS)
SNR/SFDR (dB)
70 65 60
SFDR (dBc) +25C
SFDR (dBc) -40C
SNR (dB) +25C
SNR (dB) -40C 55 50
07101-028
0
10
20
30
40
50
60
70
80
90
100
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 6. 64k Point Single-Tone FFT; 200 MSPS, 10.3 MHz
Figure 9. Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 1.25 V p-p Full-Scale; 200 MSPS
100
0 -20 -40 -60 -80 -100 -120 -140 200MSPS 70.3MHz @ -1.0dBFS SNR: 62.5dB ENOB: 10.2 BITS SFDR: 77dBc
90 80 70
SFDR (dBFS)
AMPLITUDE (dBFS)
SNR (dBFS)
SNR/SFDR (dB)
60 50 40 30 SFDR (dBc) 20 10 SNR (dB)
07101-029
0
10
20
30
40
50
60
70
80
90
100
-80
-70
-60
-50
-40
-30
-20
-10
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
Figure 7. 64k Point Single-Tone FFT; 200 MSPS, 70.3 MHz
0 -20 -40 -60 -80 -100 -120 -140 200MSPS 170.3MHz @ -1.0dBFS SNR: 61.3dB ENOB: 10.1 BITS SFDR: 73dBc
6.0 5.5 5.0
Figure 10. SNR/SFDR vs. Input Amplitude; 140.3 MHz
AMPLITUDE (dBFS)
OFFSET (mV)
4.5 4.0 3.5 3.0 2.5 2.0 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
100
07101-030
0
10
20
30
40
50
60
70
80
90
FREQUENCY (MHz)
TEMPERATURE (C)
Figure 8. 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz
Figure 11. Offset vs. Temperature
Rev. 0 | Page 13 of 28
07101-012
07101-032
0 -90
07101-031
AD9230-11
1.0 0.8 0.6 0.4
1.0 0.8 0.6 0.4
DNL (LSB)
INL (LSB)
07101-034
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 OUTPUT CODE 1536 2048
0.2 0 -0.2 -0.4 -0.6 -0.8 0 512 1024 OUTPUT CODE 1536 2048
07101-033
-1.0
Figure 12. DNL
Figure 14. INL
2.5
2.0
1.5
GAIN (%FS)
1.0
0.5
0
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 13. Gain vs. Temperature
07101-013
-0.5 -60
Rev. 0 | Page 14 of 28
AD9230-11 EQUIVALENT CIRCUITS
AVDD
AVDD 25k 1k
CSB
1.2V CLK+ 10k 10k CLK-
07101-006
Figure 15. Clock Inputs
Figure 18. Equivalent CSB Input Circuit
AVDD
DRVDD
VIN+ 2k AVDD BUF 2k BUF VCML ~1.4V BUF AVDD
V+ Dx- V-
V- Dx+ V+
VIN-
Figure 16. Analog Inputs (VCML = ~1.4 V)
07101-007
Figure 19. LVDS Outputs (Dx+, Dx-, OR+, OR-, DCO+, DCO-)
AVDD SCLK/DFS RESET PWDN 25k 1k
DRVDD
1k SDIO/DCS 25k
07101-011
Figure 17. Equivalent SCLK/DFS, RESET, PWDN Input Circuit
07101-008
Figure 20. Equivalent SDIO/DCS Input Circuit
Rev. 0 | Page 15 of 28
07101-010
07101-009
AD9230-11 THEORY OF OPERATION
The AD9230-11 architecture consists of a front-end sampleand-hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 11-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a buffered differential SHA that can be ac- or dc-coupled. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state.
Differential Input Configurations
Optimum performance is achieved while driving the AD9230-11 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
1V p-p 49.9 499 499 523 0.1F 33 499 33 AVDD VIN+
AD8138
20pF
AD9230-11
VIN-
07101-014
07101-015
CML
Figure 21. Differential Input Configuration Using the AD8138
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9230-11 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN- should be matched such that common-mode settling errors are symmetrical. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal. A wideband transformer, such as Mini-Circuits(R) ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Both analog inputs are selfbiased by an on-chip resistor divider to a nominal 1.4 V. An internal differential voltage reference creates positive and negative reference voltages that define the 1.25 V p-p fixed span of the ADC core. This internal voltage reference can be adjusted by means of SPI control. See the Configuration Using the SPI section.
VCC
At input frequencies in the second Nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the AD9230-11. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz and excessive signal power can also cause core saturation, leading to distortion. In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.
15 1.25V p-p 50 2pF VIN+
AD9230-11
VIN-
15 0.1F
Figure 22. Differential Transformer--Coupled Configuration
As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver can be used (see Figure 23).
0.1F 0.1F ANALOG INPUT 0 16 1 2 200 CD RD RG 3 ANALOG INPUT 0.1F 0 4 5 14 0.1F
07101-016
8, 13 11
0.1F
R VIN+ C R
AD8352
10 0.1F
200
AD9230-11
VIN- CML
0.1F
Figure 23. Differential Input Configuration Using the AD8352
Rev. 0 | Page 16 of 28
AD9230-11
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230-11 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and the CLK- pin via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 24 shows a preferred method for clocking the AD9230-11. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9230-11 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9230-11 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance.
MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1F XFMR 100 0.1F 0.1F SCHOTTKY DIODES: HSM2812
In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 27). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V (as shown in Figure 28), making the selection of the drive logic voltage very flexible.
0.1F
CLK
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
OPTIONAL 0.1F 100
CLOCK INPUT
50*
CMOS DRIVER
CLK
CLK+
AD9230-11
CLK-
ADC
0.1F
0.1F
*50 RESISTOR IS OPTIONAL.
39k
07101-020
0.1F CLOCK INPUT 50
CLK+
AD9230-11
CLK-
07101-017
ADC
Figure 27. Single-Ended 1.8 V CMOS Sample Clock
Figure 24. Transformer-Coupled Differential Clock
CLOCK INPUT
0.1F CLK 50*
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
OPTIONAL 0.1F 100
*50 RESISTOR IS OPTIONAL.
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CLOCK INPUT 0.1F CLK PECL DRIVER CLK 50* 50* 240 240
07101-018
Figure 28. Single-Ended 3.3 V CMOS Sample Clock
0.1F CLK+ 100 0.1F
Clock Duty Cycle Considerations
AD9230-11
CLK-
ADC
CLOCK INPUT
0.1F
*50 RESISTORS ARE OPTIONAL.
Figure 25. Differential PECL Sample Clock
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CLOCK INPUT 0.1F CLK LVDS DRIVER CLK 50* 50*
07101-019
0.1F CLK+ 100 0.1F
CLOCK INPUT
0.1F
ADC AD9230-11
CLK-
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9230-11 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9230-11. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Configuration Using the SPI section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate.
*50 RESISTORS ARE OPTIONAL.
Figure 26. Differential LVDS Sample Clock
Rev. 0 | Page 17 of 28
07101-021
If a low jitter clock is available, another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 25. The AD9510/AD9511/AD9512/AD9513/ AD9514/AD9515 family of clock drivers offers excellent jitter performance.
CMOS DRIVER CLK
CLK+
0.1F
0.1F
AD9230-11
CLK-
ADC
AD9230-11
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 x log10[1/2 x x fA x tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 29). Treat the clock as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9230-11. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com).
130 120 110 100
SNR (dB)
DIGITAL OUTPUTS
Digital Outputs and Timing
The AD9230-11 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SPI. This LVDS standard can further reduce the overall power dissipation of the device, which reduces the power by ~39 mW. See the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9230-11 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 30. Figure 31 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is up to the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches.
07101-022
RMS CLOCK JITTER REQUIREMENT
16 BITS 14 BITS 12 BITS 10 BITS 8 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
90 80 70 60 50 40 30 1
14 500 400 300 12
TIE JITTER HISTOGRAM (Hits)
Figure 29. Ideal SNR vs. Input Frequency and Jitter
VOLTAGE (mV)
POWER DISSIPATION AND POWER-DOWN MODE
The power dissipated by the AD9230-11 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. By asserting PWDN (Pin 29) high, the AD9230-11 is placed in standby mode or full power-down mode, as determined by the contents of Register 0x08. Reasserting the PWDN pin low returns the AD9230-11 to its normal operational mode. An additional standby mode is supported by means of varying the clock input. When the clock rate falls below 20 MHz, the AD9230-11 assumes a standby state. In this case, the biasing network and internal reference remain on, but digital circuitry is powered down. Upon reactivating the clock, the AD9230-11 resumes normal operation after allowing for the pipeline latency.
10 8 6 4 2 0 -40
200 100 0 -100 -200 -300 -400 -500 -3 -2 -1 0 1 2 3
-20
0 TIME (ps)
20
40
TIME (ns)
Figure 30. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR-4
Rev. 0 | Page 18 of 28
07101-023
AD9230-11
600 12 400 TIE JITTER HISTOGRAM (Hits) 10
OR DATA OUTPUTS 1 1111 1111 0 1111 1111 0 1111 1111 +FS - 1 LSB OR
-FS + 1/2 LSB
VOLTAGE (mV)
200
8
-200
4
-FS -FS - 1/2 LSB
+FS +FS - 1/2 LSB
Figure 32. OR Relation to Input Voltage and Output Data
-400
2
TIMING
0 TIME (ps) 100
07101-024
-600 -3
-2
-1
0
1
2
3
0 -100
TIME (ns)
The AD9230-11 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9230-11. These transients can degrade the dynamic performance of the converter. The AD9230-11 also provides data clock output (DCO) intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO. The lowest typical conversion rate of the AD9230-11 is 40 MSPS. At clock rates below 1 MSPS, the AD9230-11 assumes the standby mode.
Figure 31. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An example of the output coding format can be found in Table 12. If it is desired to change the output data format to twos complement, see the Configuration Using the SPI section. An output clock signal is provided to assist in capturing data from the AD9230-11. The DCO is used to clock the output data and is equal to the sampling clock (CLK) rate. In single data rate mode (SDR), data is clocked out of the AD9230-11 and must be captured on the rising edge of the DCO. In double data rate mode (DDR), data is clocked out of the AD9230-11 and must be captured on the rising and falling edges of the DCO See the timing diagrams shown in Figure 2 and Figure 3 for more information.
RBIAS
The AD9230-11 requires the user to place a 10 k resistor between the RBIAS pin and ground. This resister should have a 1% tolerance and is used to set the master current reference of the ADC core.
Output Data Rate and Pinout Configuration
The output data of the AD9230-11 can be configured to drive 12 pairs of LVDS outputs at the same rate as the input clock signal (single data rate, or SDR, mode), or six pairs of LVDS outputs at 2x the rate of the input clock signal (double data rate, or DDR, mode). SDR is the default mode; the device can be reconfigured for DDR by setting Bit 3 in Register 14 (see Table 13).
CONFIGURATION USING THE SPI
The AD9230-11 SPI allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC. This gives the user added flexibility to customize device operation depending on the application. Addresses are accessed (programmed or readback) serially in 1-byte words. Each byte may be further divided down into fields, which are documented in the Memory Map section. There are three pins that define the serial port interface (SPI) to this particular ADC. They are the SCLK/DFS, SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used to synchronize the read and write data presented to the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles (see Table 9).
Out-of-Range (OR)
An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OR has the same pipeline latency as the digital data. OR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in Figure 32. OR remains high until the analog input returns to within the input range and another conversion is completed. By logically AND-ing OR with the MSB and its complement, overrange high or underrange low conditions can be detected.
Rev. 0 | Page 19 of 28
07101-025
0
0 0 1
6
0000 0000 0000 0000 0000 0000
AD9230-11
Table 9. Serial Port Interface Pins
Mnemonic SCLK Function SCLK (serial clock) is the serial shift clock in. SCLK is used to synchronize serial interface reads and writes. SDIO (serial data input/output) is a dual-purpose pin. The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. CSB (chip select bar) is an active low control that gates the read and write cycles. Master Device Reset. When asserted, device assumes default settings. Active low.
HARDWARE INTERFACE
The pins described in Table 9 comprise the physical interface between the user's programming device and the serial port of the AD9230-11. All serial pins are inputs, which is an opendrain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 k). This interface is flexible enough to be controlled by either PROMS or PIC microcontrollers as well. This provides the user with an alternate method to program the ADC other than using an SPI controller. If the user chooses not to use the SPI interface, some pins serve a dual function and are associated with a specific function when strapped externally to AVDD or ground during device power on. The Configuration Without the SPI section describes the strappable functions supported on the AD9230-11.
SDIO
CSB RESET
The falling edge of CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 33 and Table 11. During an instruction phase, a 16-bit instruction is transmitted. Data then follows the instruction phase and is determined by the W0 and W1 bits, which is 1 or more bytes of data. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. Data can be sent in MSB or in LSB first mode. MSB first is default on power-up and can be changed by changing the configuration register. For more information about this feature and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, at www.analog.com.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers, the SDIO/DCS and SCLK/DFS pins can alternately serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. In this mode, the CSB pin should be connected to AVDD, which disables the serial port interface. Table 10. Mode Selection
Mnemonic SDIO/DCS SCLK/DFS External Voltage AVDD AGND AVDD AGND Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled
tDS tS
CSB
tHI tDH tLO
tCLK
tH
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON'T CARE
Figure 33. Serial Port Interface Timing Diagram
Rev. 0 | Page 20 of 28
07101-027
AD9230-11
Table 11. Serial Timing Definitions
Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO tDIS_SDIO Timing (minimum, ns) 5 2 40 5 2 16 16 1 5 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 33) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 33)
Table 12. Output Data Format
Input (V) VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- VIN+ - VIN- Condition (V) < 0.62 = 0.62 =0 = 0.62 > 0.62 + 0.5 LSB Offset Binary Output Mode D10 to D0 0000 0000 000 0000 0000 000 0000 0000 000 1111 1111 111 1111 1111 111 Twos Complement Mode D10 to D0 1000 0000 000 1000 0000 000 0000 0000 000 0111 1111 111 0111 1111 111 OR 1 0 0 0 1
Rev. 0 | Page 21 of 28
AD9230-11 MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), transfer register map (Address 0xFF), and ADC functions map (Address 0x08 to Address 0x2A). The Addr. (Hex) column of the memory map indicates the register address in hexadecimal, and the Default Value (Hex) column shows the default hexadecimal value that is already written into the register. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x09, the clock register, has a hexadecimal default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The default value enables the duty cycle stabilizer. Overwriting this default so that Bit 0 = 0 disables the duty cycle stabilizer. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, at www.analog.com.
RESERVED LOCATIONS
Undefined memory locations should not be written to other than their default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
Coming out of reset, critical registers are preloaded with default values. These values are indicated in Table 13. Other registers do not have default values and retain the previous value when exiting reset.
LOGIC LEVELS
An explanation of logic level terminology follows: "bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
TRANSFER REGISTER MAP
Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears.
Table 13. Memory Map Register
Addr. Bit 7 (Hex) Register Name (MSB) Chip Configuration Registers 0x00 chip_port_config 0 Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 Default Value (Hex) 0x18 Notes/ Comments The nibbles should be mirrored by the user so that LSB-or MSB-first mode registers correctly, regardless of shift mode. Default is unique chip ID, different for each device. This is a read-only register. Child ID used to differentiate graded devices. Synchronously transfers data from the master shift register to the slave.
0x01
chip_id
8-bit chip ID, Bits[7:0] AD9230-11 = 0x0C
Readonly
0x02
chip_grade
0
0
0
Speed grade: 11 = 200 MSPS
X
X
X
Readonly
Transfer Register 0xFF device_update
0
0
0
0
0
0
0
SW transfer
0x00
Rev. 0 | Page 22 of 28
AD9230-11
Addr. (Hex) Register Name ADC Functions 0x08 modes Bit 7 (MSB) 0 Bit 6 0 Bit 5 PWDN: 0 = full (default) 1= standby Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 0x00 Notes/ Comments Determines various generic modes of chip operation.
0x09
clock
0
0
0
0
0x0D
test_io
0
0
Reset PN23 gen: 1 = on 0 = off (default)
Reset PN9 gen: 1 = on 0 = off (default)
0x0F
ain_config
0
0
0
0
0x14
output_mode
0
0
0
0x15
output_adjust
0
0
0
Output enable: 0= enable (default) 1= disable 0
Internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) Note: external PWDN pin overrides this setting 0 0 0 Duty cycle stabilizer: 0= disabled 1= enabled (default) Output test mode: 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checker board output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (Format determined by output_mode) 0 CML 0 Analog enable: input disable: 1 = on 0 = off 1 = on (default) 0 = off (default) Data format select: Output DDR: 00 = offset binary invert: 1= (default) 1 = on enabled 01 = twos 0 = off 0= complement disabled (default) 10 = gray code (default) LVDS course adjust: 0= 3.5 mA (default) 1= 2.0 mA 0 0 LVDS fine adjust: 001 = 3.50 mA 010 = 3.25 mA 011 = 3.00 mA 100 = 2.75 mA 101 = 2.50 mA 110 = 2.25 mA 111 = 2.00 mA 0
0x01
0x00
When this register is set, the test data is placed on the output pins in place of normal data.
0x00
0x00
0x00
16
output_phase
Output clock polarity 1= inverted 0= normal (default)
0
0
0
0x03
Rev. 0 | Page 23 of 28
AD9230-11
Addr. (Hex) 0x17 Register Name flex_output_delay Bit 7 (MSB) Output delay enable: 0= enable 1= disable 0 Bit 6 0 Bit 5 0 Bit 4 Bit 2 Bit 1 Output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns ... 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns Input voltage range setting: 10000 = 0.98 V 10001 =1.00 V 10010 = 1.02 V 10011 =1.04 V ... 11111 = 1.23 V 00000 = 1.25 V 00001 = 1.27 V ... 01110 = 1.48 V 01111 = 1.50 V 0 0 OR position (DDR mode only): 0 = Pin 9, Pin 10 1= Pin 21, Pin 22 Bit 3 Bit 0 (LSB) Default Value (Hex) 0 Notes/ Comments
0x18
flex_vref
0
0
0
0x2A
ovr_config
0
0
0
0
OR enable: 1 = on (default) 0 = off
0x01
Rev. 0 | Page 24 of 28
AD9230-11 OUTLINE DIMENSIONS
8.00 BSC SQ 0.60 MAX 0.60 MAX
43 42
0.30 0.23 0.18
56 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
7.75 BSC SQ
EXPOSED PAD (BOTTOM VIEW)
4.45 4.30 SQ 4.15
0.50 0.40 0.30
29 28
14 15
0.30 MIN 6.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
SEATING PLANE
0.50 BSC
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
100808-A
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 34. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm x 8 mm Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9230BCPZ11-200 1 AD923011-200EBZ1
1
Temperature Range -40C to +85C
Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] LVDS Evaluation Board
Package Option CP-56-2
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
AD9230-11 NOTES
Rev. 0 | Page 26 of 28
AD9230-11 NOTES
Rev. 0 | Page 27 of 28
AD9230-11 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07101-0-10/08(0)
Rev. 0 | Page 28 of 28

▲Up To Search▲

Price & Availability of AD9230-11

	To Download AD9230-11 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .